1. Technical Field
The present invention relates to a latch circuit of a display apparatus, a display apparatus, electronic equipment, and the like.
2. Related Art
For example, in matrix-type display apparatuses in which electro-optical elements such as liquid crystal elements or organic EL elements are arranged in a matrix, data sequentially transmitted via a serial interface is latched, for example, by a data latch circuit according to a shift clock from a shift register. Data for one line on a display panel is latched by the data latch circuit. When all data for one line is latched by the data latch circuit, the data for one line from the data latch circuit is simultaneously latched by a line latch circuit according to a horizontal synchronizing signal. In this manner, data for one line on the display panel is acquired (Refer to, for example, FIGS. 6 to 8 of JP-A-2004-334105).
According to a layout in the related art, a data latch circuit for sequentially latching data for one line and a line latch circuit for simultaneously latching data for one line are spaced away from each other. However, this layout is problematic in that an interconnect connecting these latch circuits becomes long, and tends to be affected by noise.
In recent years, for example, a driver including a latch circuit can be installed in a display panel such as an LCOS panel or an Si-OLED (organic light-emitting diode) panel in which a liquid crystal layer is formed on a silicon substrate. In this case, the latch circuit is formed in consideration of a pixel pitch of display pixels formed in the display panel. The reason for this is to make it easy to establish interconnection, by arranging a latch element for latching data that is to be supplied to one pixel, within the width of that pixel.
However, for example, in the case of a micro display panel used for a display such as an electronic viewfinder (EVF) or a head-mounted display (HMD), the pixel pitch is as small as, for example, 2.5 μm.
Furthermore, as the number of gradation bits in one pixel increases, the number of interconnects connecting data latch circuits and line latch circuits increases. Thus, the area occupied by the latch circuits increases.
Accordingly, there is an additional problem that it is difficult to arrange a latch element for latching data that is to be supplied to one pixel of a display panel, within the width of that pixel.